基于自给时钟的高精度Sigma-Delta ADC设计

Design of Self-Timed High Precision Sigma-Delta ADC

为了在电源管理芯片中完成高精度、低功耗的模数转换,提出了1种自给时钟的增量型Sigma-Delta模数转换器(ADC).该ADC由2阶Sigma-Delta调制器结构组成,使用基于过零检测的开关电容积分器代替了基于运算放大器的开关电容积分器,又通过2阶积分器电路的相互触发产生自给时钟,从而无需外部提供时序信号.该ADC使用0.5μm CMOS工艺,在运行500个周期时可以获得的信号噪声失真比(SNDR)为90.06 d B,有效精度为14.66位,转换时间小于330μs,在5 V供电下功耗为0.317 m W.在保持Sigma-Delta ADC较高精度的同时,通过采用基于零点检测的电路减少了所需的外围电路,从而节省了面积.

In order to accomplish analog to digital conversion with high-precision and low-power consumption in battery management chip, a self-timed second-order incremental ADC is proposed. This ADC consists of zero-crossing detection based switched capacitor integrators instead of operational amplifier based integrators. It uses a clock-free second-order Sigma-Delta modulator structure, in which the two integrators trigger each other. While maintaining high accuracy, the Sigma-Delta ADC has reduced power consumption and conversion time by using zero- based detection circuit. The ADC is fabricated in 0.5 μm CMOS and has a conversion time less than 330 μs with oversampling ratio of 500. It consumes 0.317 m W from a 5 V supply.