H.264解码器中帧内预测模块的硬件设计

Intra Prediction Module Design in H. 264 Decoder

为了消除图像编码过程中出现的空间冗余,H.264编码器采用了帧内预测技术提高压缩率。而在解码过程中,帧内预测解码部分占用了较多的时钟资源和硬件资源。本文针对协议中帧内预测编码的算法,通过分析,对算法进行化简,并根据邻块的空间相关性特点,设计了一种并行结构。经过功能验证与FPGA验证,表明该解码模块在消耗硬件资源增加17%的基础上,可以比常规解码模块提高45%的解码速度,较好的满足性能要求。

In order to reduce the distance redundancy in the H. 264 encoding, intra prediction is used to improve compression ratio. However, the intra prediction module takes a lot of clock cycles and chip area in decoding process. This paper analyzes the intra pre- diction algorithm in the H. 264 standard and simplifies the decoding process. For the distance dependency of neighbor block, a parallel structure is designed. The results of verification on FPGA shows this decoding module is able to improve the 45% decoding speed while only imports 17% FPGA resources.