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FPGA设计中软硬件自动协同仿真平台的搭建及验证 被引量:1

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摘要 随着FPGA设计功能越来越强、器件结构越来越复杂,其验证的复杂度就越来越高。对于一个大规模FPGA设计,其逻辑验证的效率和可靠性往往决定了任务的成败。本文介绍了一种软硬件自动协同仿真平台的搭建,在此平台上对AES算法的RTL实现进行测试验证,与传统RTL级验证相比,软硬件协同仿真大大提高了逻辑验证的验证效率和测试覆盖率。
作者 董巍 李广才
出处 《数字技术与应用》 2016年第3期81-82,共2页 Digital Technology & Application
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参考文献8

  • 1JBhasker.!VerilogHDLSynthesisAPracticalPrimer[M].北京:清华大学出版社.2004.
  • 2Michael D Ciletti. Advanced Digital Design With the Verilog HDL[M].Beijing, China: Pub. House of Electronics Industry,2004.
  • 3SamirPalnitkar.夏字闻,胡燕祥.刁岚松,等译.夏字闻审校.VerilogHDL数字设计与综合(第2版)[M].北京:电子工业出版社.2007.
  • 4曹晓丽,王爱强.AES算法研究[J].洛阳师范学院学报,2011,30(8):74-75. 被引量:6
  • 5Kshirsagar, Vyawahare. FPGA Implementations of AES Algorithm [C].IEEE Electronics Computer Technology,201 1,3(3):401-405.
  • 6Xinmiao Zhang,ParhiK K.High-speed VLSl architectures for the AES algorithm.Very Large Scale Integration(VLSl)Systems, IEEE transactions onVolumel2,1ssue 9,Sept.2004:957.
  • 7章立生,韩承德,等.SoC芯片设计方法及标准化[J].计算机研究与发展,2002,39(1):1-8. 被引量:17
  • 8G.Martin, B.Bailey and A.Piziali, ESL Design and Verification: A Prescription forElectronic System Level Methodology(System on Silicon)[M].Morgan Kaufmann.March 9,2007.

二级参考文献40

  • 1崔建双,李铁克,张文新.对称加密算法Rijndael及其编程实现[J].计算机工程,2004,30(13):89-91. 被引量:10
  • 2沈昌祥,张焕国,冯登国,曹珍富,黄继武.信息安全综述[J].中国科学(E辑),2007,37(2):129-150. 被引量:358
  • 3C Lennard. Enabling VC exchange through system-level VC standards. In: Proc of Forum on Design Language. Lyon, France, 1999
  • 4Christopher K Lennard et al. Standard for system level design: Practical, reality or solution in search of a question? In: Proc of the Design, Automation and Test in Europe Conf. Paris, France, 2000
  • 5K Kücükcakar. Analysis of merging core-based design lifecycle. In: ICCAD'98. San Jose, California, 1998
  • 6VSI Alliance. VSIA Architecture Document, Version 1.0. 1997. http:∥www.vsi.org/library/vsi-or.pdf
  • 7D Cottrell, D Mallis, J Morrell. CHDStd-A model for deep submicron design tools. In: Proc of Asia and South Pacific Design Automation Conf. Yokohama, Japan, 1998
  • 8P Flake, S Davidmann. Superlog, a unified design language for system-on-chip. In: Proc of the Asia South-Pacific Design Automation Conf. Yokohama, Japan, 2000
  • 9L Lavagno, E Sentovich. ECL: A specification environment for system-level design. In: Proc of the 36th Design Automation Conf. New Orleans, LA, 1999
  • 10C Liao, S Tjiang, R Gupta. An efficient implementation of reactivity for modeling hardware in the scenic design environment. In: Proc of the 34th Design Automation Conf. Anaheim, California, 1997

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