高速串行数据处理模块的设计与实现

Design and Implementation of High-speed Serial Data Processing Module

为提高现有密码模块中数据加解密算法的多样性和安全性,设计并实现一种基于双现场可编程门阵列(FPGA)与数字信号处理器(DSP)架构的数据处理模块。2片FPGA分别与DSP通过外部存储器接口(EMIF)总线进行互联。FPGA 1#利用PCIe,EMIF总线实现其与上位机和DSP的通信,并结合分散-收集型直接内存存取模块最大化PCIe链路带宽。FPGA 2#使用AURORA协议与FPGA 1#进行串行通信,实现多个加解密算法的并行工作,同时支持算法的全局和局部重构。DSP负责数据加解密算法的参数配置、密钥生成与安全管理。在中标麒麟操作系统下的板级功能与性能验证结果表明,该模块与主机的通信速率可达11.36 Gb/s,同时具有密码安全性高和算法可重构的特点,适用于高速数据协同处理领域。

In order to improve the diversity and safety of data encryption and decryption algorithms in cryptographic modules,this paper designs and implements a data processing module based on dual Field Programmable Gate Array （FPGA） and Digital Signal Processor （DSP） architecture. Two pieces of FPGA are interconnected with a DSP by External Memory Interface（EMIF） bus. FPGA 1# communicates with PC and DSP by PCIe and EMIF bus,and Scatter- gather Direct Memory Access （SG-DMA） is used for high-speed data transferring application. FPGA 2# realizes serial communication with FPGA 1 # by AURORA protocol, makes multiple algorithms work in parallel, and supports global and partial reconfiguration of the algorithm. DSP realizes parameter configuration as well as＇key generation and management for data encryption and decryption algorithms. The driver and application software are designed on NeoKylin operating system to test the module＇ s function and performance. Results show that the rate of communication between the module and the host is up to 11.36 Gb/s, and the module has the characteristics of high safety and reconfiguration suitable for high-speed data co-processing field.