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基于正交设计的WLCSP柔性无铅焊点随机激励应力应变分析 被引量:4

Stress and strain distribution of lead-free solder joints with compliant layer in wafer level chip scale package under random vibration based on orthogonal design
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摘要 对晶圆级芯片尺寸封装(wafer level chip scale package,WLCSP)柔性无铅焊点进行了随机振动应力应变有限元分析.以1号柔性层厚度、2号柔性层厚度、上焊盘直径和下焊盘直径4个结构参数作为关键因素,采用正交表设计了16种不同结构参数组合的柔性焊点,获取了16组应力数据并进行了方差分析.结果表明,焊点内最大应力应变随1号柔性层厚度和2号柔性层厚度的增加而减小;在置信度99%时,下焊盘直径和上焊盘直径对应力具有高度显著影响,在置信度95%时,1号柔性层厚度和2号柔性层厚度对应力具有显著影响;各因素对应力影响排序为:下焊盘直径影响最大,其次是上焊盘直径,再次是1号柔性层厚度,最后是2号柔性层厚度. The 3D finite element analysis models of leadfree solder joint with compliant layer in wafer level chip scale package( WLCSP) were developed. By using ANSYS the finite element analysis of the lead-free solder joints model was performed under random load. 1st compliant layer thickness,2nd compliant layer thickness,die-side and substrate-side pad diameter were selected as four key configuration parameters,by using orthogonal array,the solder joints which have 16 different configuration parameters ' levels combinations were designed. The maximum stress values within lead-free solder joints were obtained. Based on the values of stress the range analysis was performed. The results of study show that the stress and strain decreases with the increase of 1st and 2nd compliant layer thickness. With 99% confidence,the substrate-side pad diameter and die-side pad diameter have significant effect on the stress of solder joint under random vibration load,and with 95% confidence,the 1st compliant layer thickness and the 2nd compliant layer thickness have a certain effect on the stress of solder joint.The substrate-side pad diameter,the die-side pad diameter,the1 st compliant layer thickness and the 2nd compliant layer thickness affect the stress of solder joints in a descending order.
出处 《焊接学报》 EI CAS CSCD 北大核心 2016年第2期13-16,129,共4页 Transactions of The China Welding Institution
基金 国家自然科学基金资助项目(51465012) 广西壮族自治区自然科学基金资助项目(2015GXNSFCA139006 2013GXNSFAA019322) 四川省教育厅科研资助项目(13ZB0052)
关键词 晶圆级芯片尺寸封装 柔性无铅焊点 随机振动 有限元分析 方差分析 Wafer level chip scale package lead-free solder joint with compliant layer random vibration finite element analysis variance analysis
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参考文献7

  • 1Lee C C, Chang S M, Chiang K N. Sensitivity design of DL-WLCSP using DOE with factorial analysis technology [ J ]. IEEE Transac- tions on Advanced Packaging, 2007, 30 (1) : 44 -55.
  • 2Watanabe N, Asano T. Characteristics of a novel compliant bump for 3-D stacking with high-density inter-chip connections [ J ]. IEEE Transactions on Packaging and Manufacturing Technology. 2011, 1(1): 83- 91.
  • 3Tanaka S, Mohri M, Ognshiwa T, et al. Electrical interconnection in anodic bonding of silicon wafer to LTCC wafer using highly com- pliant porous bumps made from submicron gold particles [ C ]/// Sensors and Actuators A: Physical, 2012:1 -5.
  • 4Naoya W, Tanemaza A. A large number of I/O connections using compliant bump[ J]. Electronic Components and Technology Con- ference, 2006, 6 : 125 - 130.
  • 5Fan X J, Varia B, Hart Q. Design and optimization of thermo-me- chanical reliability in wafer level packaging [ J ]. Micmelectronics Reliability. 2010, 50(4) : 536 -546.
  • 6Lu S T, Lin Y M, Chuang C C, eta/. Development of a novel compliant-bump structure for ACA-bonded chip-on-flex (COF) in- terconnects with ultra-fine pitch [ J ]. IEEE Transactions on Com- ponents, Packaging and Manufacturing Technology, 2011, 1 ( 1 ) : 33 -42.
  • 7郭强,赵玫,孟光.随机振动条件下SMT焊点半经验疲劳寿命累积模型[J].振动与冲击,2005,24(2):24-26. 被引量:13

二级参考文献7

  • 1Wu J D, Ho S H, etc. Board level reliability of a stacked CSP subjected to cyclic bending [J],Microelectronic Reliability, 42 (2002),407-416
  • 2Tong Yan Tee, Hun Shen Ng, etc. Board level solder joint reliability modeling and testing of TFBGA packages for telecommunication application [J], Microelectronics Reliability, (43)2003,1117-1123
  • 3Amagai M. Chip Scale Package(CSP)solder joint reliability and modeling [J], Microelectronics Reliability,(39) 1999,463-477
  • 4Tong Yan Tee, Hun Shen Ng, etc. Comprehensive board-level solder joint reliability modeling and testing of QFN and Power QFN Packages [J], Microelectronics Reliability,(43) 2003, 1329-1338
  • 5Dave S .Steinberg, Vibration Analysis for Electronic Equipment [M],Second Edition ,A Wiley-Interscience Publication,JOHN WILEY & SONS, 1989
  • 6刘祁,何琳,束立红.随机载荷下疲劳寿命预估计算方法研究[J].海军工程大学学报,2002,14(2):31-33. 被引量:4
  • 7王红芳,赵玫,孟光.塑封焊球阵列焊点三维形态预测及其“整体”近似优化设计[J].上海交通大学学报,2002,36(6):829-833. 被引量:1

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