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Direct tunneling gate current model for symmetric double gate junctionless transistor with SiO_2/high-k gate stacked dielectric

Direct tunneling gate current model for symmetric double gate junctionless transistor with SiO_2/high-k gate stacked dielectric
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摘要 A junctionless transistor is emerging as a most promising device for the future technology in the decananometer regime. To explore and exploit the behavior completely, the understanding of gate tunneling current is of great importance. In this paper we have explored the gate tunneling current of a double gate junctionless transistor(DGJLT) for the first time through an analytical model, to meet the future requirement of expected high-k gate dielectric material that could replace SiO2. We therefore present the high-k gate stacked architecture of the DGJLT to minimize the gate tunneling current. This paper also demonstrates the impact of conduction band offset,workfunction difference and k-values on the tunneling current of the DGJLT. A junctionless transistor is emerging as a most promising device for the future technology in the decananometer regime. To explore and exploit the behavior completely, the understanding of gate tunneling current is of great importance. In this paper we have explored the gate tunneling current of a double gate junctionless transistor(DGJLT) for the first time through an analytical model, to meet the future requirement of expected high-k gate dielectric material that could replace SiO2. We therefore present the high-k gate stacked architecture of the DGJLT to minimize the gate tunneling current. This paper also demonstrates the impact of conduction band offset,workfunction difference and k-values on the tunneling current of the DGJLT.
出处 《Journal of Semiconductors》 EI CAS CSCD 2016年第3期37-41,共5页 半导体学报(英文版)
关键词 junctionless transistor direct tunneling gate current model high-k gate stacked dielectric junctionless transistor direct tunneling gate current model high-k gate stacked dielectric
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  • 1Lo S H, Buchanan D A, Taur Y, et al. Quantum mechanical mod- eling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFET's. IEEE Electron Device Lett, 1997, 18(5): 209.
  • 2Campbell S A, Gilmer D C, Wang X C, et al. MOSFET transis- tors fabricated with high permittivity TiO2 dielectric. IEEE Trans Electron Devices, 1997, 44(1): 104.
  • 3Robertson J. High dielectric constant oxides. Eur Phys J Appl Phys, 2004, 28(3): 265.
  • 4Kizilyaili I C, Roy P K, Baumann F, et al. Stacked gate dielectrics with TaO for future CMOS technologies. Proc VLSI Symp Tech- nology, 1998:216.
  • 5Wilk G D, Wallace R M, Anthony J M. High-k gate dielectrics: current status and materials properties considerations. J Appl Phys, 2001, 89(10): 5243.
  • 6Cheng B, Cao M, Rao R, et al. The impact ofhigh-k gate dielec- tric and metal gate electrodes on sub-100 nm MOSFET's. IEEE Trans Electron Devices,' 1999, 46(7): 1537.
  • 7Kauerauf T, Govoreanu B, Degraeve R, et al. Scaling CMOS: finding the gate stack with the lowest leakage current. Solid-State Electron, 2005, 49(5): 695.
  • 8Zhao Y, White M H. Modeling of direct tunneling current through interracial oxide and high-k gate stacks. Solid-State Electron, 2004, 48(10/11): 1801.
  • 9Wang W, Gu N, Sun J P, et al. Gate current modeling ofhigh-k stack nanoscale MOSFETs. Solid-State Electron, 2006, 50(9/10): 1489.
  • 10Li F, Mudanai S P, Fan Y Y, et al. Physically based quantum-mechanical compact model of MOS devices substrate-injected tunneling current through ultrathin (EOT 1 nm) SiO2 and high- k gate stacks. IEEE Trans Electron Devices, 2006, 53(5): 1096.

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