摘要
在选择特定CMOS工艺基础上,本文提出了同步Buck型转换器开关桥拓扑结构和器件最佳组合的选择方法。DC-DC转换器是集成在有着相同负载的集成电路中,集成电路工作点已知且恒定。本文设计空间由多种共源共栅/非共源共栅开关桥拓扑结构和可用MOS开关器件构成,由本文方法选出的设计空间,满足使电源转换效率η最大化的设计要求。本文提出的方法缩小了设计空间、找到了最低功耗组合,并且避免了繁琐的比较仿真工作。在45nm和65nm CMOS工艺基础上,本文对具有核心器件、I/O器件和高压器件的同步3.3-1.65V Buck型转换器进行仿真。仿真结果与理论值（由本文方法计算所得）对比结果验证了本文提出方法的可行性。此外,通过对比得到的结论对于以后详细设计和相关拓扑结构优化提供有效参考。
This paper offers a way to find the best selection of synchronous buck converter switching bridge topology and equipment in the selection of CMOS technology.It is assumed that the DC-DC converter is on the same integrated circuit where the load has a constant operating point that is known.The design space consists of the variety of cascode/noncascode switch bridge topologies and available MOS switch devices.The goal of maximizing the power efficiencyηis met with a very large design space.To avoid exhaustive simulations,the proposed technology-independent approximation method narrows down the design space and suggests the most power-efficient combination.Synchronous3.3~1.65 V Buck converters simulations with core,I/O,and HV devices in 45 and 65-nm CMOS technologies confirmed that the method produces reliable comparative results.Furthermore,the outcome is a sharp focus for subsequent detailed dc-dc converter design and topology-dependent optimization.
出处
《电子测量技术》
2016年第2期33-37,共5页
Electronic Measurement Technology
