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An analytical model for nanowire junctionless SOI FinFETs with considering three-dimensional coupling effect 被引量:2

An analytical model for nanowire junctionless SOI Fin FETs with considering three-dimensional coupling effect
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摘要 In this paper, the three-dimensional (3D) coupling effect is discussed for nanowire junctionless silicon-on-insulator (SOI) FinFETs. With fin width decreasing from 100 nm to 7 nm, the electric field induced by the lateral gates increases and therefore the influence of back gate on the threshold voltage weakens. For a narrow and tall fin, the lateral gates mainly control the channel and therefore the effect of back gate decreases. A simple two-dimensional (2D) potential model is proposed for the subthreshold region of junctionless SO1 FinFET. TCAD simulations validate our model. It can be used to extract the threshold voltage and doping concentration. In addition, the tuning of back gate on the threshold voltage can be predicted. In this paper, the three-dimensional (3D) coupling effect is discussed for nanowire junctionless silicon-on-insulator (SOI) FinFETs. With fin width decreasing from 100 nm to 7 nm, the electric field induced by the lateral gates increases and therefore the influence of back gate on the threshold voltage weakens. For a narrow and tall fin, the lateral gates mainly control the channel and therefore the effect of back gate decreases. A simple two-dimensional (2D) potential model is proposed for the subthreshold region of junctionless SO1 FinFET. TCAD simulations validate our model. It can be used to extract the threshold voltage and doping concentration. In addition, the tuning of back gate on the threshold voltage can be predicted.
出处 《Chinese Physics B》 SCIE EI CAS CSCD 2016年第4期344-352,共9页 中国物理B(英文版)
基金 supported by the Research Program of the National University of Defense Technology(Grant No.JC 13-06-04)
关键词 coupling effect threshold voltage subthreshold region SOI FinFETs junctionless front gate lateral gate back gate coupling effect, threshold voltage, subthreshold region, SOI FinFETs, junctionless, front gate,lateral gate, back gate
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