中值滤波算法的研究及其FPGA实现

Research on median filtering algorithm and its implementation of FPGA

对已有的传统中值滤波算法、快速中值滤波算法进行了基于FPGA设计实现.在此基础上提出了快速中值滤波的一种改进算法,并进行了设计.3种中值算法都利用Verilog HDL进行编程,通过对比仿真结果,表明了改进算法在达到较好的滤波效果的同时在硬件实现上的优越性.

Based on FPGA, the traditional median filtering algorithm and fast median filtering algorithm aredesigned and implemented. On this basis, an improved algorithm of fast median filter is proposed and thecomparison is made with the two previous algorithms. Three algorithms are programmed by HDL Verilog, and thesimulating results show the superiority of the improved algorithm on hardware implementation.