高速串行数据传输链路中固定延时设计

Design of Fixed-Latency for High-Speed Serial Data Links

在高能物理实验中,由于需要预测数据传输时间,触发器和高速数据传输系统需要具有固定延时的串行链路。然而,当前嵌入在最新一代可编程逻辑门阵列(FPGA)中的高速收发器通常是不带固定延时能力的。给出了基于LOCic编解码器的固定延时传输设计。讨论了LOCic解码器中帧头位置鉴别寄存器与数据串行传输相位延时间的关系。实验和测试结果表明给出的固定延时设计简单,可靠可行。

In high energy physics（HEP） experiments,the trigger and data acquisition system requiring a predictable data transfer timing need the fixed-latency serial links.However,at present,the high-speed transceivers embedded in the latest generation FPGAs are typically designed for applications without fixed latency.The scheme of the serial link with fixed latency based on LOCic encoder and decoder is proposed.The relation between the frame header position identification register value in the LOCic decoder and latency phase is also discussed.Experimental and test results show that the fixed latency of the link is stabile and valid.