基于双位触发器的低功耗技术研究

Research on low power technology based on Multi Bit Flip Flop

随着工艺水平的不断发展以及集成电路的特征尺寸不断减小,目前集成电路已经跨入了超深亚微米的SOC设计阶段,芯片也朝着面积更小、性能更强、功耗更低的方向发展。由于手持设备不断更新换代以及对低功耗有着迫切的需求,关于低功耗的研究成果层出不穷。在后端设计流程中使用双位触发器已经成为目前一种降低时钟网络功耗的有效方法。在标准单元级别,由于双位触发器共用时钟资源,相比两个单位触发器少用了一对反相器。在物理实施阶段,由于双位触发器的使用导致时钟节点的减少,进一步减少时钟树综合阶段所用的缓冲器。这两方面都有效的减少了面积以及降低了功耗。本文将在设计流程中采用双位触发器的方案,并分析双位触发器使用对设计流程各个阶段的影响。

With the development in the process and the characteristic size reduced continuously, the integrated circuit has entered the design phase of SOC ultra deep sub micron and it also towards smaller, higher performance, low power consumption development. With the continuous upgrading of handheld devices and lower power consumption, there is an urgent need for the research on low power consumption. The use of multi-bit flip flop（MBFF） has been shown to be an effective design technique to reduce power consumption of clock network.In the level of standard cell, one MBFF share resources and use two less inverter compared to two SBFFs. In the phase of physical implementation, the reduced number of clock sinks resulting in a simper clock network and less clock buffer. Both of these two level has reduced area and power consumption efficiently. The paper will take the flow with MBFF and analyzes the effect on different phase.