用于新型塑料闪烁体阵列探测器的多通道前端读出电子学设计

Design of Multi-channel Front-end Readout Electronics Applied for New Plastic Scintillator Array Detector

介绍一种用于新型塑料闪烁体阵列探测器系统的前端读出电子学(FEE)的设计与实现,该前端读出电子学主要基于电荷测量专用的集成电路(ASIC)芯片和现场可编程逻辑门阵列(FPGA)研制,可实现对多路探测器信号的采集、处理、筛选、打包,并通过LVDS差分接口上传到后端的数据获取系统(DAQ)。同时,该电路设有板载线性标定电路,可实现对各通道电子学性能刻度,设有电源电流、关键芯片及电路温度实时监控等电路,使电路具有较完善的功能和较强的自我保护能力。

The circuit and control logic design for new front-end readout electronics（FEE）,which was based on a kind of ASIC chip and field-programmable gate array（FPGA）,was described in this paper.The FEE was mainly applied in a new plastic scintillator array detector and it can sample,process and filtrate the 360 channels of analog signals from the new plastic scintillator array detector,then package and upload data from the detector to the data acquisition system（DAQ）through the LVDS differential interface.Meanwhile,with the circuits of linearity calibration for each channel,monito-ring current of power supply,temperature of key devices and FPGA＇s status parameters,the FEE has a set of useful functions and strong ability of self-protection.