基于FPGA的高速固态存储器优化设计

Optimization Design of High-speed Solid-state Memory Based on FPGA

针对雷达信号采集系统中高采样率和ADC(模数转换器)带宽产生的海量数据的高速存储问题,对基于FPGA控制的LVDS(低压差分信号)高速数据通信接口的NANDFLASH为存储介质的高速固态存储器进行了优化设计。高速固态存储器采用了均衡加重、交替双平面交叉编程的分时加载技术操作、基于FPGA的二级缓存和三线组合指令等优化措施,平均存储速度不小于59 MB/s。高速固态存储器已成功应用于某导弹发射数据回收试验,优化设计的可行性和可靠性已通过工程实践验证。

In view of the high speed storage problem of high sampling rate and ADC bandwidth generate massive amounts of date in radar signal system,and for NANDFLASH FPGA-based control LVDS（low voltage differential signaling）high-speed data communication interface for high-speed solid-state memory storage medium optimized design.High-speed solid-state memory with a balanced emphasis,alternating bi-planar cross programmed load sharing technical operations,FPGA-based secondary cache and three lines combined instruction and other optimization measures,the average memory speed not less than 59 MB/s. High-speed solid-state memory has been successfully applied to a missile launch data recovery test and optimize the design of the feasibility and reliability has been proven by the project.