基于VHDL-AMS的流水线ADC结构式建模方法与仿真

Constructral Modeling Method and Simulation for Pipeline ADC Using VHDL-AMS

目前很多模数转换器(ADC)缺乏仿真模型,为了大型模数混合信号系统建模与仿真的需要,提出一种基于VHDL模拟混合信号扩展(VHDL Analog and Mixed-Signal Extensions,VHDL-AMS)的流水线ADC结构式建模方法.以多比特位每级的12位分辨率、10 MSPS流水线ADC作为建模对象,根据流水线ADC的结构特征,在考虑非理想因素误差情况下,分别建立采样保持放大和乘法数模转换器的VHDL-AMS子模型,然后通过例化建立顶层流水线ADC的结构模型.通过SystemVision和Simulink联合仿真,得到静态性能参数微分非线性度和积分非线性度均小于1LSB,动态性能参数无杂散动态范围94.941 7dB,总谐波失真-94.941 9dB,信噪比58.754 4dB,验证了所提建模方法合的理与有效.

A large amount of analog-to-digital converters （A D C） lack of simulation model now, a constructral modeling method for pipeline ADC using VHDL Analog and Mixed-Signal Extensions （VHDL-AMS） is proposed in this paper in order to meet the necessary of modeling and simulation of large analog/mixed signal system. Multi-bit/ stage 12 bit, 10 MSPS pipeline ADC is taken as modeling object, accroding to its architectural character, the VHDL-AMS sub-model of Sample-Hold Amplifier and Multiplying Digital to Analog Converter is built respectively with taking account of nonideal factors, and then the architectural model of high level pipeline ADC is built by instantiating. By the co-simulation of SystemVision and Simulink, intatic performance parameter Differential Non- Linearity （DNL） and Integral Non-Linearity （INL） are all less than 1 LSB; dynamic performance parameter Spurious Free Dynamic Range （SFDR） is 94. 9417 dB, Total Harmonic Distortion （THD） is -94. 9419 dB, Signal to Noise Ratio （SNR） is 58. 7544 dB. The result shows that the proposed modeling method is reasonable and verified.