一种高电源抑制低温漂带隙基准电路设计

Design of High Power Supply Rejection and Low Temperature Drift Voltage Bandgap Reference

基于CSMC0．5μmBCD工艺，设计了一种应用于片上系统（SOC）芯片的低温漂高电源抑制的带隙基准电路．采用一种带有负反馈环路调整型的电压预调整电路，并且将基准电压形成于负反馈环路，基准电路的电源抑制特性得到显著提高．仿真得到的电源抑制比分别为-177．6dB@dc，-82．7dB@1MHz．此电路可以在-55～125℃范围内实现较小的温度系数，温度系数为5．76×10^（-6）／℃．

Based on a CSMC 0. 5μm BCD process, a high power supply rejection and low temperature drift bandgap voltage reference is proposed for the application of system-on-chip. By introducing a pseudo-power supply and generating a voltage reference in a negative feedback loop, the power supply rejection of the reference is improved. This voltage reference provides a PSR of --177. 6 dB at dc and -82.7 dB at 1MHz. Additionally, the temperature coefficient of this circuit achieves 5.76×10^（-6）/℃ covering a range of -55-125℃.