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一种超低功耗高性能的亚阈值全CMOS基准电压源 被引量:3

An Ultra Low Power and High Performance CMOS-Only Voltage Reference Based on Subthreshold
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摘要 介绍了一种超低功耗、无片上电阻、无双极型晶体管(BJT)的基于亚阈值CMOS特性的基准电压源,该带隙基准源主要用于低功耗型专用集成电路(ASIC)。采用Oguey电流源结构来减小静态电流,以降低功耗。通过使用工作在线性区的MOS管代替传统结构中的电阻消除迁移率和电流的温度影响,同时减小芯片面积;采用共源共栅电流镜以降低电源电压抑制比和电压调整率。电路基于SMIC 0.18μm CMOS工艺进行仿真。仿真结果表明,在-45~130℃内,温漂系数为29.1×10-6/℃,电源电压范围为0.8~3.3 V时,电压调整率为0.056%,在100 Hz时,电源电压抑制比为-53 d B。电路功耗仅为235 n W,芯片面积为0.01 mm2。 An ultra low power voltage reference based on the characteristics of the CMOS subthreshold region without resistors and bipolar junction transistor( BJT) was presented for low power application-specific integrated circuits( ASICs). In order to reduce the power dissipation,an Oguey current reference source was used to reduce the static current. The MOSFET operated in linear region which instead of the ordinary resistors,was used to eliminate the impact of the mobility and current temperature,and decrease the chip area. The power supply rejection ratio( PSRR) and the line regulation were reduced by a cascode current mirror. The circuit was simulated based on SMIC 0. 18 μm CMOS process.The simulation results show that the temperature coefficient of the voltage is 29. 1 × 10- 6/ ℃ in a range of- 45 ℃ to 130 ℃. The line regulation is 0. 056% in a supply voltage range of 0. 8 V to 3. 3 V,and PSRR is- 53 d B at 100 Hz. The power dissipation is only 235 n W. The chip area is 0. 01 mm2.
出处 《半导体技术》 CAS CSCD 北大核心 2016年第4期261-266,共6页 Semiconductor Technology
基金 国家自然科学基金资助项目(61161003 61264001 61166004) 广西自然科学基金资助项目(2013GXNSFAA019333) 广西桂林电子科技大学研究生科研创新项目(YJCXS201519)
关键词 专用集成电路(ASIC) 超低功耗 电压基准源 亚阈值 电源电压抑制比(PSRR) 共源共栅电流镜 application-specific integrated circuit(ASIC) ultra low power dissipation voltage reference source subthreshold power supply rejection ratio cascode current mirror
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参考文献15

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