摘要
采用大规模可编程数字逻辑器件FPGA/CPLD设计新型的时序逻辑电路实现数字电路实验平台,其实验内容上具有较好的开放性,使数字电路设计由硬件设计向软件化设计方向发展,改善了传统的以中小规模为主的实验教学模式,增强了学生的创新能力和动手能力。文章对基于可编程器件的数字电路实验教学系统进行了具体的研究。
The paper uses large-scale programmable digital logic device FPGA/CPLD to design a new type of sequential logic circuit and digital circuit experiment platform, which makes the experiment content have good openness and changes the design of digital circuit design from the hardware to software design direction. The paper tries to improve the traditional small and medium-sized experiment teaching mode and enhance the students' innovation ability and practice ability. The paper concretely studies on the digital circuit experiment teaching system based on programmable device.
出处
《江苏科技信息》
2016年第7期36-37,共2页
Jiangsu Science and Technology Information
基金
西南科技大学实验室开放基金项目
项目编号:14xnkf08
2015年度电子信息类专业教指委"重大
热点
难点问题"研究课题
项目编号:2015-Y6