一种基于数字DAC校准的低失调动态比较器

A low-offset dynamic comparator with calibration based on digital DAC

提出一种基于二进制加权电容DAC阵列的比较器校准技术,并基于该技术65nm CMOS工艺下设计实现了一款低功耗高精度动态比较器。基于版图数据的模拟仿真结果表明,在1.2V的工作电压下,该校准技术可以将失调电压降低至0.25mV以下,功耗为0.33μW,功耗开销增大57%。

We propose a calibration technique based on binary capacitor DAC.We also design a lowpower high-precision dynamic comparator using 65 nm CMOS technology.Simulation results based on layout show that our proposal can reduce the offset less than 0.25 mV under 1.2Vsupply.It achieves 0.33μW power dissipation,an increase of 57%in comparison with the comparators without calibration.