基于Viterbi的低功耗确定性测试方案

Low Power Deterministic Test Scheme Based on Viterbi

随着集成电路制造技术的不断发展,芯片测试已经成为一个令人关注的热点.针对集成电路测试中存在测试数据量大、测试功耗高等问题,提出一种基于Viterbi的低功耗测试压缩方案.首先利用测试立方的X位做低功耗填充来增强解码后测试模式相邻位之间的一致性;然后以增加测试立方中的X位为目标进行分段相容编码,将填充后的大量确定位重新编码为X位,从而提高Viterbi压缩中种子的编码效率;最后利用Viterbi算法压缩编码后的测试立方集.整体方案以分段相容编码思想为基础,建立了一个协同解决测试压缩和测试功耗问题的测试流程.实验结果表明,文中方案不仅能取得较好的测试数据压缩率,减少测试存储量,而且能够有效地降低测试功耗,平均功耗降低53.3%.

With the development of integrated circuit manufacturing technology, chip test has become a focus ofconcern. For the problem of a large amount of test data volume and high test power consumption, this paper proposesa low power test compression scheme based on Viterbi algorithm. Firstly, a few don’t care bits（X bits） intest cubes are used to reduce test power, for enhancing the consistency between adjacent bits of the cube. Then inorder to increase the number of X bits and improve the encoding efficiency of Viterbi compression, lots of specifiedbits are encoded to X bits again by compatible block code. Finally, use Viterbi algorithm to compress the testcube set after coding. This paper presents a test process that can solve the problems of test compression and testpower at the same time. The experimental results show that the scheme not only obtains better test compression ratio, but also reduces the test power consumption effectively. The average power consumption is reduced by53.3%.