基于时钟控制技术的低功耗三值D触发器设计

Design of ternary D-type flip-flop based on clock-gating technique

提出一种低功耗的基于时钟控制技术的三值D触发器(CG-TDFF)。CG-TDFF通过在电路中嵌入时钟控制技术,在输入信号不发生改变时抑制时钟链以减少触发器内部节点的冗余跳变,从而有效地降低电路功耗。基于SMIC65 nm工艺的仿真结果表明,CG-TDFF具有正确的逻辑功能,低功耗特征明显,在开关活动性为10%时,功耗比参考电路下降最高达29.84%。

A low power ternary D-type flip-flop based on clock-gating technique （CG-TDFF） is proposed. The proposed design employs a clock-gated control circuit in the pulse generating stage. When the input stays unchanged, the clock inverter is blocked, which in turns reduces the redundant transition of internal nodes, resulting in great power reduction. Based on the SMIC65 nm process tech- nology, the simulation results prove that the proposed design exhibits correct logic functionality and low power character. And at 10% data switching activity,the proposed design gains a power reduction up to 29.84% against its rival design.