一种精度可编程的低功耗SAR ADC

A Low Power SAR ADC with Reconfigurable Resolution

设计了一种精度可编程的低功耗逐次逼近型模数转换器(SAR ADC)。采用电阻电容混合结构的数模转换(DAC)阵列,通过对低位电阻阵列的编程控制,实现了12,10,8位的转换精度,对应不同的精度,电路支持1,5,10 MS/s的转换速率。采用一种改进的单调开关控制逻辑以降低功耗和面积,同时避免了原有单调开关逻辑存在信号馈通的缺点。根据不同的精度要求,对比较器所用预放大器的个数进行编程控制,进一步提高了ADC的功耗效率。电路基于0.18μm的CMOS工艺设计,在1.8V电源电压下,精度从高到低对应的功耗分别为0.56,0.48,0.42mW;SNDR分别为73.2,61.3,48.2dB;SFDR分别为96.3,84.6,62.8dB。芯片内核面积仅为(0.6×0.9)mm^2,适用于通用片上系统(SoC)。

A low power SAR ADC with reconfigurable resolution was presented.The R-Chybrid DAC array was used in this ADC.The reconfigurable resolutions of 12,10,8bit were realized by controlling the lower resistorarray.The ADC supported variable conversion rates of 1,5and 10 MS/s for each of the resolutions.An improved monotonic switching procedure was proposed to reduce the power consumption and area occupation of the circuit.Meanwhile,the signal feed-through in the conventional monotonic switching procedure could be avoided.The number of the preamplifiers in the comparator was programmed according to the different resolution of the ADC.Then the power efficiency of the ADC could be improved further.The SAR ADC was designed in a 0.18μm CMOS technology and had a core area of（0.6×0.9）mm^2.The power consumption of the ADC was 0.56,0.48 and 0.42 mW for each of the resolutions of 12,10 and 8bit with a 1.8V supply voltage.The SNDR was 73.2,61.3,48.2dB,and the SFDR was 96.3,84.6,and 62.8dB respectively.It was suitable for the general SoC applications.