DDR2 SDRAM控制器IP功能测试与FPGA验证

Function Simulation and FPGA Verification of DDR2 SDRAM Controller IP

完成挂载在AHB上对DDR2SDRAM进行操作的DDR2控制器IP模块的设计,并通过了相关的读写测试。利用Altera的Qsys平台,将得到的DDR2控制器IP挂载到NiosII上,搭建SoPC系统,完成软硬件协同验证。验证结果表明,该IP在StratixIV的FPGA核心芯片上共占用287个逻辑单元,DDR2的工作频率可达200MHz。同时,开发出了一套将AHB总线接口的IP挂载到NiosII Avalon总线上进行FPGA验证的通用方法。

The DDR2 controller module IP mounted on AHB bus was designed to control the DDR2 SDRAM operation.Relevant read and write tests were accomplished.Moreover,the DDR2 controller IP was connected to NiosII CPU based on Altera’s Qsys platform.The SoPC system had completed hardware and software coverification.Results showed that 287 ALUTs of StratixIV FPGA core chip were occupied and the DDR2 SDRAM operating frequency was up to 200 MHz.Meanwhile,a set of method was developed to connect IP with AHB bus interface to NiosII’s Avalon bus and implement the FPGA verification.