一种40nm MOSFET版图相关的波动模型建立

Modeling of a 40nm MOSFET Layout-Related Volatility

针对版图邻近与工艺波动因素对40nm MOSFET器件物理效应变化和性能波动的影响进行分析,提出一种基于BSIM4.5的新型模型,修正原有模型的阈值电压和迁移率机制,有效地实现了版图邻近效应的建模。该模型主要考虑了相邻栅极间距psf和pss,相邻有源区的横向间距sodx1和sodx2,以及纵向间距sody对器件性能的影响。基于国内先进的40nm工艺平台,对器件的V_(thsat),I_(dsat),V_(thlin)和I_(dlin)性能进行监测,得到相邻栅极间距对饱和电流和阈值电压分别有15%和30mV的影响,横纵向有源区间距对饱和电流和阈值电压分别有1.5%和4mV的影响,从而得到拟合度较好的仿真模型。结果表明,建立的模型能够有效降低结构仿真误差,大大提高设计人员的设计效率和准确性。

A new compact and scalable Spice model based on BSIM4.5 for the layout proximity effects of poly gate in 40 nm MOSFET was proposed.The impacts of neighboring gate space and neighboring active space on mobility and threshold voltage had been taken into account in this model.With the 40 nm silicon verification,Vthsat,Idsat,Vthlinand Idlinwere monitored.The saturation current changed up to 15% and the threshold voltage changed up to 30 mV due to the impact of gate space.The saturation current changed up to 1.5% and the threshold voltage changed up to 4mV due to the impact of active space.The proposed model had achieved an excellent goodness of fit.These good results showed that the model could reduce effectively the structure simulation errors,and the efficiency and accuracy of layout design were improved greatly for the circuit designers.