期刊文献+

Research and Design of Reconfigurable Composite Field Multiplication in Symmetric Cipher Algorithms 被引量:1

Research and Design of Reconfigurable Composite Field Multiplication in Symmetric Cipher Algorithms
原文传递
导出
摘要 The composite field multiplication is an important and complex module in symmetric cipher algorithms, and its realization performance directly restricts the processing speed of symmetric cipher algorithms. Based on the characteristics of composite field multiplication in symmetric cipher algorithms and the realization principle of its reconfigurable architectures, this paper describes the reconfigurable composite field multiplication over GF((2^8)k) (k=1,2,3,4) in RISC (reduced instruction set computer) processor and VLIW (very long instruction word) processor architecture, respectively. Through configuration, the architectures can realize the composite field multiplication over GF(2^8), GF ((2^8)2), GF((28)3) and GF((28)4) flexibly and efficiently. We simulated the function of circuits and synthesized the reconfigurable design based on the 0.18 μm CMOS (complementary metal oxide semiconductor) standard cell library and the comparison with other same kind designs. The result shows that the reconfigurable design proposed in the paper can provide higher efficiency under the premise of flexibility. The composite field multiplication is an important and complex module in symmetric cipher algorithms, and its realization performance directly restricts the processing speed of symmetric cipher algorithms. Based on the characteristics of composite field multiplication in symmetric cipher algorithms and the realization principle of its reconfigurable architectures, this paper describes the reconfigurable composite field multiplication over GF((2^8)k) (k=1,2,3,4) in RISC (reduced instruction set computer) processor and VLIW (very long instruction word) processor architecture, respectively. Through configuration, the architectures can realize the composite field multiplication over GF(2^8), GF ((2^8)2), GF((28)3) and GF((28)4) flexibly and efficiently. We simulated the function of circuits and synthesized the reconfigurable design based on the 0.18 μm CMOS (complementary metal oxide semiconductor) standard cell library and the comparison with other same kind designs. The result shows that the reconfigurable design proposed in the paper can provide higher efficiency under the premise of flexibility.
出处 《Wuhan University Journal of Natural Sciences》 CAS CSCD 2016年第3期235-241,共7页 武汉大学学报(自然科学英文版)
基金 Supported by the National Natural Science Foundation of China(61202492,61309022,61309008) the Natural Science Foundation for Young of Shaanxi Province(2013JQ8013)
关键词 RECONFIGURABLE composite field multiplication symmetric cipher algorithm RISC VLIW (very long instruction word) reconfigurable composite field multiplication symmetric cipher algorithm RISC VLIW (very long instruction word)
  • 相关文献

参考文献1

二级参考文献10

  • 1Menezes A J,Oorscho P C V,Vanstone S A.Handbook of Applied Cryptography,Boca Raton,FL,CRC Press,1997.
  • 2Orlando G.Efficient elliptic curve processor architectures for field programmable logic[PhD thesis].Dept.of Electrical Eng.,Worcester Polytechnic Institute,America,2002.
  • 3Bednara M,Daldrup M,Gathen J V Z.Reconfigurable implementation of elliptic curve crypto algorithms.parallel and distributed processing symposium.Proceedings International,IPDPS,Fort Lauderdale,Florida 2002:157-164.
  • 4Mastrovito E.VLSI architectures for computation in Galois fields[PhD thesis].Dept.of Electrical Eng.,Linkoping Univ.,Sweden,1991.
  • 5Lee C Y,Lu E H,Sun L F.Low-complexity bit-parallel systolic architecture for computing AB2 + C in a class of finite field GF(2m).IEEE Trans.on Circuits and Systems Ⅱ,2001,48(5):519-523.
  • 6Paar C,Fleischmann P,Rordriguez P S.Fast arithmetic for public-key algorithms in Galois fields GF(2m) with composite exponents.IEEE Trans.on Computers,1999,38(7):796-800.
  • 7Moon S,Park J,Lee Y.Fast VLSI arithmetic algorithms for high-security cryptographic application.IEEE Trans.on Consumer Electronics,2001 47(3):700-708.
  • 8Kitsos P,Theodoridis G,Koufopavlou O.An efficient reconfigurable multiplier architecture for GF(2m).Microelectronic Journal,2003,34(10):975-980.
  • 9Hasan M A,Ebtedaei M.Efficient architectures for computations over variable dimensional Galois fields.IEEE Trans.on Circuits andSystems I,1998,45(11):1205-1211.
  • 10Beth T,Gollman D.Algorithm engineering for public key algorithms.IEEE J.on Selected Areas in Communications,1989,7 (4):466-485.

共引文献3

同被引文献3

引证文献1

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部