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基于热点行搜索的低功耗数据高速缓存 被引量：1

Low Power Data Cache Based on Hotspot Initiative Search
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摘要 针对数据高速缓存短时间内频繁访问连续区段的特征,该文提出了一种基于热点硬件自搜索和历史访问轨迹的数据高速缓存低功耗方法.该方法通过动态搜索热点片段,缓存目标热点行在高速缓存中的位置信息,过滤标签存储器和冗余数据存储器的访问.运行EEMBC测试基准的实验结果表明,与基于MRU(Most Recently Used)的路预测方法相比,该方法 Cache的动态功耗可降低30.77%,性能提升26.21%. On account of the characteristics that the data cache will be frequently accessed in a short period of time,this paper proposes a lowpower data cache access methods based on hotspot initiative search and historical access trace. The method will automatically judge hot process,dynamically buffer the target hotspot location information to filter tag and redundant data memory access. Running EEMBC benchmark results showthat compared with MRU prediction method（ Most Recently Used） this approach can reduce 30. 77% dynamic access power,and get 26. 21% performance improvement.
作者 仇径 罗嘉蕙 项晓燕 陈志坚
机构地区 浙江大学超大规模集成电路设计研究所 复旦大学专用集成电路与系统国家重点实验室
出处 《电子学报》 EI CAS CSCD 北大核心 2016年第1期110-114,共5页 Acta Electronica Sinica
关键词 低功耗 过滤访问 热点行搜索 lowpower filter access hotspot initiative search
分类号 TP302.2 [自动化与计算机技术—计算机系统结构] TN47 [电子电信—微电子学与固体电子学]
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参考文献13

  • 1Zang W,Gordon-Ross A. A survey on cache tuning from a power/energy perspective [J]. ACM Computing Surveys (CSUR) ,2013,45(3) :32.
  • 2ZHENG Z, Zhiying W, Li S. Region-based way-partitioning on L1 data cache for low power[ J] IEICE Transactions on Information and Systems, 2013,96 ( 11 ) : 2466 - 2469.
  • 3Xiangyun Z, Lianfeng Z, Dong B. Research on the low power design method for the embedded multi-core proces- sor[ A]. 2013 Fourth International Conference on Digital Manufacturing and Automation (ICDMA) [C ]IEEE, 2013. 1141 - 1144.
  • 4Inoue K, Ishihara T, Murakami K. Way-predicting set-asso- ciative cache for high performance and low energy con- sumption[ A]. Proceedings of the 1999 International Sym- posium on Low Power Electronics and Design [ C ] ACM, 1999. 273 - 275.
  • 5Chen H C. Design of a low-power way-predicting cache u- sing valid-bit pre-decision strategy [ J ]. Journal of the Chi- nese Institute of Engineers, 2008,31 (5) : 805 - 814.
  • 6Ye J, Ding H, Hn Y, et al. A behavior-based adaptive ac- cess-mode for low-power set-associative caches in embed- ded systems [ J ]. Journal of Information Processing, 2012, 20( 1 ) :26 - 36.
  • 7Kin J, Gupta M, Mangione-Smith W H. The filter cache:an energy efficient memory structure [ A] . Proceedings of the 30th Annual ACM/IEEE International Symposium on Micr- oarchitecture[ C ] IEEE Computer Society ,1997. 184 - 193.
  • 8Yang C L,Lee C H. HotSpot cache:joint temporal and spatial locality exploitation for i-cache energy reduction [ A]. Pro- ceedings of the 2004 International Symposium on Low PowerElectronics and Design[ C]. IEEE,21304. 114 - 119.
  • 9Fan L, Wang S, Zheng Y, et al. Low power cache architec- tures with hybrid approach of filtering unnecessary way ac- cesses[ A]. Proceedings of the 2013 International Work- shop on Programming Models and Applications for Mul- ticores and Manycores [ C ]. ACM, 2013.93 - 99.
  • 10张宇弘,王界兵,严晓浪,汪乐宇.标志预访问和组选择历史相结合的低功耗指令cache[J].电子学报,2004,32(8):1286-1289. 被引量：6

二级参考文献22

  • 1R Gonzalez,M Horowitz.Energy dissipation in general purpose microprocessors.IEEE Journal of Solid State Circuits[J].1996,31(9):1277-1284.
  • 2E Witchel,S Larsen,C Ananian, K Asanovi'c.Direct addressed caches for reduced power consumption[A].Proc.of the 34th Int.Symp.On Microarchitecture[C].Austin,Texas,2001.124-134.
  • 3R Panwar,D Rennels.Reducing the frequency of tag compares for low power i-cache design[A].Proc of the 1995 Int Symp on Low Power Electronics and Design[C].New York,1995.57-62.
  • 4J Montanaro et al.A 160-MHz,32-b,0.5-W CMOS RISC Microprocessor[J].In IEEE ISSCC,1996,31(11):1703-1714.
  • 5K Inoue,T Ishihara, K Murakami.Way-predicting set-associative cache for high performance and low energy consumption[A].In Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED)[C].San diego,CA,USA,1999.273-275.
  • 6D H Albonesi.Selective cache ways:On-demand cache resource allocation[A].Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 32)[C].Haifa,ISRAEL.1999.248-259.
  • 7B Batson,T N Vijaykumar.Reactive associative caches[A].Proceedings of the 2001 International Conference on Parallel Architectures and Compiliation[C].Barcelona,Spain,2001.49-60.
  • 8J Kin,M Gupta, W H Mangione-Smith.The filter cache:An energy efficient memory structure[A].In Proceedings of the 30th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 30)[C].Research Triangle Park,North Carolina.1997.184-193.
  • 9S Manne,A Klauser,D Grunwald.Pipline gating:Speculation control for energy reduction[A].Proceedings of the 25th Annual International Symposium on Computer Architecture[C].Barcelona,Spain,1998.132-141.
  • 10M Gowan,L Biro, D Jackson.Power considerations in the design of the alpha 21264 microprocessor[A].In 35th Design Automation Conference[C].New York.1998.726-731.

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