基于TSV绑定的三维芯片测试优化策略

Optimization Strategy for TSV-Based 3D SoC Testing

本文提出一种三维片上系统(3D So C)的测试策略,针对硅通孔(TSV,Through Silicon Vias)互连技术的3D So C绑定中和绑定后的测试进行优化,由于测试时间和用于测试的TSV数目都会对最终的测试成本产生很大的影响,本文的优化策略在有效降低测试时间的同时,还可以控制测试用的TSV数目,从而降低了测试成本.实验结果表明,本文的测试优化策略与同类仅考虑降低测试时间的策略相比,可以进一步降低约20%的测试成本.

The optimization problem of three dimensional system on chip（ So C） needs to be solved before it enters the market. We propose a reconfigured test architecture optimization of TSV-based（ Through Silicon Vias-based） 3D So C,and the optimization includes both mid-bond testing and post-bond testing. As both test time and the number of TSV for test impact the overall test cost,our proposed scheme can reduce overall test time,while controlling the number of TSVs. Experiment results showthat our scheme achieves around 20% on the reduction of test cost compared with one baseline solution which only considers reducing test time.