摘要
Y2002-63070-56 0206041动态位级可收缩阵列开关级模拟用的门识别与网表简化=Gate recognition and netlist reduction for switch-lev-el simulation of dynamic bit-level systolic arrays[会,英]/Blotti,A.& Mannozzi,F.//2001 Southwest Sympo-sium on Mixed-Signal Design.—56～60(PE)
出处
《电子科技文摘》
2002年第4期21-22,共2页
Sci.& Tech.Abstract
