H.264/AVC分数运动估计改进及VLSI实现

Improvement of H.264/AVC Fractional Motion Estimation and Implement of VLSI

目前H.264/AVC采用的分数运动估计算法是先进行1/2像素插值,再进行1/4像素插值,这样会造成存储访问量增大,因此对此进行改进,提出了一种新的用于H.264分数运动估计的VLSI结构,改进分数运动估计的迭代顺序为1/2像素插值和1/4像素插值同时进行,设计出一种具有更高并行性的VLSI结构。在0.18umCMOS工艺下作了逻辑综合和仿真,相比于现有结构,这种结构能够提高系统的数据吞吐率和处理能力,降低存储访问带宽需求和系统的整体功耗。

Currently,the algorithm which H.264/AVC fractional motion estimation uses is first 1/2-pixel interpolation,and then 1/4-pixel interpolation.This results in increasing memory access store.So this paper changes this case,raise a new H.264 fractional motion estimation for VLSI architecture.Change loop order of fractional motion estimation to 1/2-pixel and 1/4-pixel interpolation at the same time,and designs a higher parallel VLSI architecture to implement fractional motion estimation.Made under the 0.18um CMOS process logic synthesis and simulation,compared with the existing architecture,this architecture can improve data throughput and processing power,reduce memory access requirements and overall system power consumption.