摘要
针对高速、高阶成型滤波器的实现问题,在传统分布式DA算法的基础上,提出一种改进算法.利用升采样过程中内插零的结构特点,使用逻辑单元LUT代替存储ROM,减少了有效地址位数,提高了寻址速度;利用表分割算法和滤波器系数的对称性,并通过增加流水线结构,进一步节约了存储资源的消耗,提升了运算速度.通过与商用FIR IP核(DA算法)的实测对比,所提算法最大实现速率有所提高,且在高阶滤波器设计时不受硬件ROM大小和数量的限制,有效改善了逻辑资源的使用情况.
In order to meet the requirement of high-speed and high-order shaping filter design, an improved DA （Distributed Architecture ） algorithm is proposed on the basis of the traditional DA method. Considering zero insertion using in up-sampling process, Look-Up-Table is employed instead of ROM （ Read-Only Memory ） for reducing the number of effective address and increasing addressing speed. The proposed algorithm takes advantage of tables segmentation and symmetry of filter coefficients to save storage resource and improve processing speed. Meanwhile, pipeline contracture is further exploited to achieve better performance. Compared with commercial finite impulse response filter IP core, the proposed algorithm not only realizes higher rate as well as reduces the utilization of logic resources effectively, but also can design hizh-order filter without limit of ROM in hardware.
出处
《哈尔滨工业大学学报》
EI
CAS
CSCD
北大核心
2016年第5期32-35,共4页
Journal of Harbin Institute of Technology
关键词
成型滤波器
分布式结构
FPGA
查找表
FIR
pulse shaping
distribute architecture
FPGA
look-up table
FIR （finite impulse response）
