H.264/AVC解码芯片体系结构与验证

Architecture and Verification for H.264/AVC Decode So C

H.264是一种高性能的视频编解码技术,在编解码效率和性能大幅提高的同时,增强了错误恢复及网络自适应等功能,具有广泛的应用前景,体系结构的合理设计与验证对H.264/AVC芯片至关重要。文中基于对H.264/AVC解码芯片体系结构的研究,构建FPGA验证平台,并对编程结构、软件框架及验证的实施进行了深入探索。首先确定了芯片的体系结构,为H.264/AVC解码芯片的设计验证提供了有力支撑,并通过搭建FPGA的测试,在FPGA对所设计的芯片功能和性能进行验证。验证结果表明,基于该体系结构的芯片功能正确,可满足实时解码需求,体系结构的设计与验证为整个芯片的设计提供了重要保障。

H.264 is a high performance video codec technology.It is enhanced in the performance and efficiency of video codec,and also improved in error recovery,network adaptive function and so on.So it has broad prospect.The raional design and verification of the architecture is very important to the H.264 / AVC SoC.Based on the research of H.264 / AVC So C architecture,it constructs FPGA verification platform,and studies the programming structure,the software framework and implementation of verification in depth.Firstly,the architecture of the SoC is designed,which provides a powerful support for the verification of H.264 / AVC Decode So C.Secondly,by building the FPGA test platform,the function and performance of the SoC is verified in FPGA.The verification results showthat the system based on the architecture is correct.It can meet the needs of real- time decoding and provides a important support for the design and verification for H.264 / AVC Decode SoC.