基于快速编码算法的QC-LDPC码编码器设计与实现

The Design and Implementation of QC-LDPC Encoder Based on Fast Encoding Algorithm

该文设计了一种低复杂度编码器并对其进行了硬件实现。该编码器针对具有准循环结构的LDPC码,利用快速迭代编码算法,在设计中只需简单的循环移位以及异或操作就可实现,因此具有较低的编码复杂度。同时针对(528,264)的QC-LDPC码,在Xilinx公司Virtex6系列的xc6vsx130t芯片上实现了该编码器设计,经过ISE软件布局布线后,结果显示编码器只消耗了280个slices资源,而编码吞吐量达到了147.168Mbps。另外利用时序仿真软件Isim进行验证,结果显示输出比输入只延迟了7个时钟,可见该算法的编码速度比较快。

This paper presents a lowcomplexity encoder and its hardware implementation.The encoder for a quasi-cyclic structure LDPC code,usesfastiterativecoding algorithminthedesignachieved bysimplecyclic shiftand XORoperation,and thereforehasalowerencoding complexity.Atthesametimeforthe（528,264） ofthe QCLDPC code,theencoderisdesignonthechip of Xilinx＇s Virtex6 series xc6vsx130 t,layoutafter the ISE software,theresultsshowtheencoderonlyconsumed 280 slicesresource,and coding throughputreached 147.168 Mbps.Inadditiontheuseoftiming simulationsoftware Isim,theoutputshowstheoutputis only delayed by seven clocks thantheinput,showing thealgorithmcoding isfaster.