2500V压接式IGBT芯片的仿真与验证

Simulation and Verification of 2 500 V Press-pack IGBT Chip

基于现有工艺平台设计一款具有自主知识产权的2 500 V/50 A非穿通型(NPT)压接式IGBT芯片。芯片有源区元胞采用平面型结构,结合器件仿真结果采用抗动态雪崩及抗闩锁设计,同时采用载流子增强技术来降低器件的饱和压降。芯片终端区采用场环加多级场板的复合结构,结合横向的场终止技术,实现高效率的终端结构设计。将此设计进行流片验证,测试结果显示击穿电压3 500 V以上,饱和压降2.65 V,阈值电压6.5 V,符合仿真预期和芯片设计要求。

A 2 500 V/50 A non punch through insulator gate bipolar transistor（NPT-IGBT） chip for press-pack with self-owned intellectual property right is designed based on the existing technology platform. The active region cell of the chip is based on the planar structure, the device simulation results are used for the chip＇s dynamic avalanche immunity design and anti-latch-up design, and the carrier enhancement technology is adopted to reduce the saturation voltage drop of the device. A guard ring and multistep field plates termination structure combined with the lateral field-stop technique is designed to improve the terminal efficiency. The test results show that the breakdown voltage is more than 3 500 V, the saturation voltage drop is 2.65 V, and the threshold voltage is 6.5 V, which meet the expected simulation results and requirement of chip design.