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软差错影响下的电路可靠性分析

Reliability Analysis of Circuit under Soft Error
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摘要 随着大数据时代的到来,人们对微处理器可靠性的要求也越来越高,同时处理器芯片内电路密度的增大使其更易受到软差错的侵害,因此软差错影响下的电路可靠性问题显得尤为重要。针对这一问题,从系统结构级、RTL、门级及电路级4个抽象层次进行了全面的分析,并在每个抽象层次上依据方法属性做了分类介绍和比较。 With the coming of the big data era,people demand more reliable microprocessor.While the intensive technology scaling make the circuit encounter greater sensitivity to soft errors.It＇s very important to analyze the reliability of the circuit under soft errors.This paper gave a survey on the reliability analysis methods,which are categorized into circuit-level,gate-level,register-transfer-level（RTL）and architecture-level,and introduced and compared these methods according to method property in each level.
作者 王真 江建慧
机构地区 上海电力学院计算机科学与技术学院 同济大学软件学院
出处 《计算机科学》 CSCD 北大核心 2016年第5期9-12,21,共5页 Computer Science
基金 国家自然科学基金重点项目(61432017) 上海电力学院人才启动基金项目(K-2013-017) 上海高校青年教师资助计划项目资助
关键词 可靠性分析 电路级 门级 RTL 系统结构级 Reliability analysis Circuit level Gate level RTL Architecture level
分类号 TP302.8 [自动化与计算机技术—计算机系统结构]
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  • 1Kim J S, Nicopoulos C, Vijakrishnan N, et al. A probabilistic model for soft-error rate estimation in combinational logic[A]. Proc. of the 1 st Int' l Workshop on Probabilistic Analysis Techniques for Real Time and Embedded Systems, Pisa[C]. New York: Elsevier, 2034.25 - 31.
  • 2Asadi G, Tahoori M B. An analytical approach for soft error rate estimation in digital circuits[ A]. IEEE Int. Symp. on Circuits and Systems, Kobe [ C ]. Hoboken: John Wiley & Sons, 2005.2991 - 2994.
  • 3Krishnaswamy S, Viamontes G F, Markov I L, et al. Accurate reliability evaluation and enhancement via probabilistic transfer matrices[A]. Proc. of the Design, Automation and Test in Europe Conference and Exhibition, Munich[C ]. New York: ACM Society, 2005.282 - 287.
  • 4Parker K P and McCluskey E J. Probabilistic treatment of general combinational networks [J]. IEEE Trans on Computers, 1975,24(6) :668 - 670.
  • 5Parker K P and McCluskey E J. Analysis of logic circuits with faults using input signal probabilities[ J]. IEEE Trans on Computers, 1975,24(5) : 573 - 578.
  • 6Ogus R C. The probability of a correct output from a combinational circuit [ J ]. IEEE Trails on Computers, 1975,24 (5) : 534 - 544.
  • 7Zarandi H R, Miremadi S G, Ejlali A R. Dependability Analysis Using a Fault Injection Tool Based on Synthesizability of HDL Models[ A]. Proc. of the 18th IEEE Int'l Symp. on Defect and Fault-Tolerance in VLSI Systems, Boston[ C]. Washington De: IEEE Computer Society,2003.485 - 492.
  • 8Leveugle R., Cimonnet:D. ,Ammari A. System-Level Dependability Analysis with RT-Level Fault Injection Accuracy[ A]. 19th IEEE Int'l Symp. on Defect and Fault Tolerance in VLSI Systems, Cannes, France, 2004 [ C ]. Los Alamitos, California: IEEE Computer Society,2004.451 - 458.
  • 9Koren I. Signal reliability of combinational and sequential circuits[A].Proc.of the 7th Int'l Symp. on Fault-Tolerant Computing,Los Angeles[C]. Washington DC: IEEE Computer Society, 1977.162 - 167.
  • 10Kwek K H and Tohma Y. Signal reliability evaluation of self-checking circuits[A] .Proc. of the 10th Int'l Syrup. on Fault- Tolerant Computing, Kyoto[C]. Washington DC: IEEE Computer Society, 1980.257 - 262.

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计算机科学
2016年 第5期

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