摘要
A low power 9 bit 100 MS/s successive approximationregisteranalog-to-digitalconverter（SARADC） with custom capacitor array is presented. A brand-new 3-D MOM unit capacitor is used as the basic capacitor cell of this capacitor array. The unit capacitor has a capacitance of 1 fF. Besides, the advanced capacitor array structure and switch mode decrease the power consumption a lot. To verify the effectiveness of this low power design, the 9 bit 100 MS/s SAR ADC is implemented in TSMC IP9M 65 nm LP CMOS technology. The measurement results demonstrate that this design achieves an effective number of bits （ENOB） of 7.4 bit, a signal-to-noise plus distortion ratio （SNDR） of 46.40 dB and a spurious-flee dynamic range （SFDR） of 62.31 dB at 100 MS/s with 1 MHz input. The SAR ADC core occupies an area of 0.030 mm2 and consumes 0.43 mW under a supply voltage of 1.2 V. The figure of merit （FOM） of the SAR ADC achieves 23.75 fJ/conv.
A low power 9 bit 100 MS/s successive approximationregisteranalog-to-digitalconverter（SARADC） with custom capacitor array is presented. A brand-new 3-D MOM unit capacitor is used as the basic capacitor cell of this capacitor array. The unit capacitor has a capacitance of 1 fF. Besides, the advanced capacitor array structure and switch mode decrease the power consumption a lot. To verify the effectiveness of this low power design, the 9 bit 100 MS/s SAR ADC is implemented in TSMC IP9M 65 nm LP CMOS technology. The measurement results demonstrate that this design achieves an effective number of bits （ENOB） of 7.4 bit, a signal-to-noise plus distortion ratio （SNDR） of 46.40 dB and a spurious-flee dynamic range （SFDR） of 62.31 dB at 100 MS/s with 1 MHz input. The SAR ADC core occupies an area of 0.030 mm2 and consumes 0.43 mW under a supply voltage of 1.2 V. The figure of merit （FOM） of the SAR ADC achieves 23.75 fJ/conv.
基金
Project supported by the National High-Tech Research and Development Program of China(No.2013AA014101)
