矩阵转置切换在FFT处理器中的应用

The application of Array Transpose Commutator in FFT processor

针对MDC架构的FFT处理器中延迟单元使用量较多的情况,介绍了一种存储器矩阵转置切换(Array Transpose Commutator--ATC)方式用以实现FFT处理器数据的存储与切换或抽取功能,与传统的MDC结构相比,可以有效减少延迟单元的使用量。并且介绍了用存储器矩阵实现UWB-OFDM系统的128点FFT处理器的方法。该128点FFT处理器采用基-(8+16)算法,硬件上采用存储器矩阵+并行蝶8运算单元+R16SDF结构,并用硬件描述语言Verilog HDL进行RTL实现,用TSMC 90 nm标准工艺库进行Design Compiler综合,得到芯片内核面积为0.6056mm^2。在52MHz频率下工作可以满足UWB-OFDM系统的要求,内核功耗为5.9mW。在1.2V,25℃条件下,最大工作时钟可达200MHz。整个处理器的控制逻辑简单,数据吞吐率大,能够满足UWB系统的要求。

In view of the situation that base on the MDC architectures, FFT processors overuse delay units, this paper presents an Array Transpose Commutator --ATC way to realize the data storage and switch or extraction functions of FFT processors. Compared with the traditional MDC structures, the ATC can reduce the usage of delay units effectively. In this paper, how to use ATC to realize 128-point FFT processor in UWB - OFDM systems is also introduced. The 128-point FFT processor adopts the R-（8＋16） algorithm, uses array transposes ＋ parallel R-8 butterfly processing elements ＋ R-16 SDF structures in hardware and realizes RTL implementation with Verilog HDL. The design is compiled by Design Compiler with 90nm TSMC technology. The kernel chip area is 0.6056 mm2. The kernel power consumption is 5.9 mW when the processor works at 52 MHz and it can meet the requirements of UWB-OFDM systems. Under the condition of 1.2 V, 25℃, the max working clock frequency can be up to 200 MHz. The control logic of the whole processor is simple, its data throughput rate is high, which can satisfy the requirements of UWB systems.