基于JESD204协议的四通道中频数字接收机的实现

Design and Implementation of Four-Channel Intermediate Frequency Digital Receiver Based on JESD204 Protocol

为满足当前雷达对宽带信号高速数据采集的需求,根据当前JESD204高速串行协议应用日益广泛的趋势,设计了一种基于高速JESD204的ADC器件、大容量FPGA为核心的四通道中频数字接收机。ADC器件实现中频信号的高速采样,FPGA主要完成JESD204协议解析和数字下变频处理。协议解析采用代码而不是FPGA的IP核实现,适用于各种FPGA和不同的JESD204协议参数。该数字接收机实现了四通道320MSPS的高速数据采集与传输,测试结果满足系统要求,电路实现简单,应用灵活。

To meet the requirement of high-speed data sampling in wideband radar, based on the trend of JESD204 protocol development and implementation in high-speed system, the circuit design of four-channel IF digital receiver is illustrated specifically with 320MSPS sampling rate, which based on JESD204 high speed serial output ADC and high-capacitance FPGA. High-speed ADC device is used to sample the IF signal, and FPGA is used to serial data processing and DDC. The JESD204 protocol is realized base on verilog code instead of FPGA IP, which is suitable for different FPGA and protocol parameters. Experiment results show that the system requirement is satisfied, and the realization if the circuit is simple and easy to be used.