基于2阶段同步的GPGPU线程块压缩调度方法

Two-Stage Synchronization Based Thread Block Compaction Scheduling Method of GPGPU

通用图形处理器(general purpose graphics processing unit,GPGPU)在面向高性能计算、高吞吐量的通用计算领域的应用日益广泛,它采用的SIMD(single instruction multiple data)执行模式使其能获得强大的并行计算能力.目前主流的通用图形处理器均通过大量高度并行的线程完成计算任务的高效执行.但是在处理条件分支转移的控制流中,由于通用图形处理器采用串行的方式顺序处理不同的分支路径,使得其并行计算能力受到影响.在分析讨论前人针对分支转移处理低效的线程块压缩重组调度方法的基础上,提出了2阶段同步的线程块压缩重组调度方法 TSTBC(two-stage synchronization based thread block compaction scheduling),通过线程块压缩重组适合性判断逻辑部件,分2个阶段对线程块进行压缩重组有效性分析,进一步减少了无效的线程块压缩重组次数.模拟实验结果表明:该方法较好地提高了线程块的压缩重组有效性,相对于其他同类方法降低了对线程组内部数据局部性的破坏,并使得片上一级数据cache的访问失效率得到有效降低;相对于基准体系结构,系统性能提升了19.27%.

The application of general purpose graphics processing unit（GPGPU）has become increasingly extensive in the general purpose computing fields facing high performance computing and high throughput.The powerful computing capability of GPGPU comes from single instruction multiple data（SIMD）execution model it takes.Currently,it has become the main stream for GPGPU to implement the efficient execution of the computing tasks via massive high parallel threads.However the parallel computing capability is affected during dealing with the branch divergent control flow as different branch path is processed sequentially.In this paper,we propose TSTBC（two-stage synchronization based thread block compaction scheduling）method based on analyzing the previously proposed thread block compaction scheduling methods in inefficient dealing with divergent branches.This method analyzes the effectiveness of thread block compaction and reconstruction via taking the use of the adequacy decision logic of thread block compaction and decreases the number of inefficient thread block compaction.The simulation experiment results show that the effectiveness of thread block compaction and reconstruction is improved to some extent relative to the other same type of methods,and the destruction on data locality inside the thread group and the on-chip level-one data cache miss rate can be reduced effectively.The performance of the whole system is increased by19.27% over the baseline architecture.