视频缩放在FPGA中的应用和实现

Application and implementation of video scaling algorithm based on FPGA

针对某显示系统中监控视频控制器的实际需求,设计了一种可实现四路视频信号实时缩放的电路架构。通过权衡几种常用图像缩放算法的显示质量和硬件可行性,选择用双线性插值算法实现视频的缩放,并在FPGA平台上以双口RAM资源构建的线缓存作为算法硬件实现,该算法主要由视频数据缓冲模块、插值系数产生模块以及整体控制模块构成。本设计在满足视频缩放质量要求的基础上,避免了采用过于复杂算法而消耗过多的FPGA资源,有效地解决了视频缩放时原始图像信息量丢失导致图像失真的问题。结果表明,该设计能够实现任意比例的视频缩放,实时性高,应用灵活,缩放后显示效果良好,能够满足实际工程的要求。

Focusing on the practical requirements of the monitoring video controller in some displaying systems, this paper introduces a circuit architecture which is designed for real time scale of four video signals. Through analyzing the display quality and hardware realizability of several scaling algorithms, selects implement video scaling by bilinear interpolation algorithm and uses line buffers architecture as the core of algorithms implementation based on FPGA. The design mainly consists of the data buffer mod-ule, the coefficient generation module and the integrated control module. To meet the quality requirements of video scaling, this design avoids selecting complex algorithms to cause FPGA resources to be consumed excessively, and effectively solves the prob-lem of image distortion caused by the loss of the original image information. The result indicates that the system can realize arbi-trary scaling, and its real- time, flexibility and display effect are good, which can meet the application requirements of the actual project.