多通道雷达数字接收机数字下变频设计

Design of multi-channel digital down-converter of digital radar receiver

提出一种基于时分复用原理的双频段多通道数字接收机DDC模块的设计方法,并利用FPGA的数控振荡器和FIR滤波器的IP核完成了DDC模块的设计与实现。仿真结果表明,该设计实现了数字混频、抽取和滤波的功能,与其他设计方案对比表明,本方案有效地减少了FPGA资源的使用量,降低了硬件设计的复杂度,节约了硬件成本。

A digital down- converter（DDC） module in a multi- channel digital radar receiver executed at two frequencies is designed based on time division multiplexing（TDM） technique, this new DDC designed by using intellectual ？ property（IP） cores of the numeri-cal controlled oscillator（NCO） and the finite impulse response（FIR） filter of a field programmable gate array（FPGA）. Simulation of this new designed DDC shows that these functions, such as digital mixer, decimation and filter have been achieved. Furthermore, this new DDC reduces the occupation of FPGA resources, simplifies the complexity of hardware design and reduces the cost of hardware.