基于SERDES的同步光纤环网设计与实现

Design and Realization of SERDES-based Synchronous Ring Fiber Net

本文介绍了一种基于SERDES的同步光纤环网的设计以及实现方法,其实现方法简单,同步效果好。通过采用FPGA中的SERDES收发器可使得信息传输速度达到1.25 Gbps,并通过链路协议有效的控制了信息在每个节点的传输延时,使得网络传输周期大大的减小,从而实现对高频率控制的支持。本文的通信协议还实现了信号采集的同步,从而提高控制精度。最终通过在硬件系统上的实验,验证了设计的正确性和可靠性。

This paper introduces a design and realization method for synchronous ring fiber net with SERDES, which very easy to realize and can reach very high synchronization. By using the SERDES core in FPGA, the communication speed can reach as fast as 1.25 Gbps, and the delay caused by each node in the ring can be significantly reduced by link protocol, which make the cycle time very short and can support high speed control. Also the paper brings up a synchronous signal acquisition method, which is very helpful in improving control accuracy. Finally, it gives the test results on hardware platform, which verify the correction and reliability of the design.