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基于动态功耗的流水线优化方法研究

Study on the pipeline optimization method based on dynamic power consumption
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摘要 流水线设计中通过增加寄存器可将毛刺进行隔离,从而降低节点的转换密度,实现动态功耗的优化,但是增加寄存器在减少毛刺的同时,不仅会增加资源消耗,而且增加的寄存器也会增加电路中的节点数量,从而产生额外的动态功耗,通过减少毛刺降低的动态功耗与增加硬件资源产生的动态功耗二者是相互矛盾的。针对此问题,通过分析毛刺和寄存器产生的动态功耗与流水线级数的变化规律,提出了基于动态功耗的流水线优化方法,并从理论上证明了优化方法的有效性。利用提出的优化方法对分形维数的计算进行优化,实验结果表明,利用提出的优化方法得到的流水线的能耗是最小的,从而验证了优化方法的有效性。 In pipeline design,adding registers can isolate glitches,therefore decrease the switching activity of the nodes,and achieve the optimization of the dynamic power consumption.However,adding registers not only increases the resource consumption,but also increases the number of nodes in the circuit while decreasing glitches,which will produce extra dynamic power consumption.The decreased dynamic power consumption through reducing glitch and the increased dynamic power consumption through adding hardware resource are contrary.Aiming at this problem,through analyzing the changing rule of the dynamic power consumption produced by glitch and registers vs.the number of pipeline stages,a pipeline optimization method based on dynamic power consumption is proposed.The effectiveness of the optimization method is proved theoretically.The proposed optimization method was used to optimize the calculation of fractal dimension.Experiment results indicate that the energy consumption of the pipeline designed using the proposed optimization method is minimum,which verifies the effectiveness of the proposed optimization method.
出处 《仪器仪表学报》 EI CAS CSCD 北大核心 2016年第5期1058-1064,共7页 Chinese Journal of Scientific Instrument
基金 山东省自然基金(ZR2014FP005) 博士科研启动基金(414007)项目资助
关键词 动态功耗 流水线 转换密度 毛刺 分形维数 dynamic power consumption pipeline switching activity glitch fractal dimension
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  • 1雷加,方刚.一种基于遗传算法的SoC测试调度方法[J].仪器仪表学报,2007,28(S1):15-17. 被引量:6
  • 2穆洪德,王峻峰,史铁林.高精度A/D转换器AD7864与DSP接口设计与实现[J].微计算机信息,2006(03Z):158-160. 被引量:12
  • 3曹琼,郑红,李行善.一种基于纹理特征的卫星遥感图像云探测方法[J].航空学报,2007,28(3):661-666. 被引量:31
  • 4张涛,孙林,黄爱民.图像分形维数的差分盒方法的改进研究[J].电光与控制,2007,14(5):55-57. 被引量:17
  • 5Narendra S, Challenges and design choices in nanoscale CMOS[J]. ACM Journal on Emerging Technologies in Computing Systems, 2005, 1(1): 7-49.
  • 6Kao J, Narendra S, and Chandrakasan A. Subthreshold leakage modeling and reduction techniques[C]. Proceedings of International Conference on Computer-Aided Design, San Jose, 2002: 141-149.
  • 7Chinnery D. High performace and low power design techniques for ASIC and custom in nanometer technology[C]. Proceedings of International Syposium on Physical Design, San Jose, 2013: 25-32.
  • 8Coudert O. Gate sizing for constrained delay/power/area optimization[J]. IEEE Transactions on Very Large Scale Integration, 1997, 5(4): 465-472.
  • 9Gupta P, Kahng A B, Sharma P, et al. Gate-length biasing for runtime-leakage control[J]. IEEE Transactions on Computer-Aided Design, 2006, 25(8): 1475-1485.
  • 10Srivastava A, Sylvester D, and Blaauw D. Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment[C]. Proceedings of Design Automation Conference, San Diego, 2004: 783-787.

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