基于键合线模拟的SiGe BiCMOS 915 MHz功率放大器的设计

Design of 915 MHz SiGe BiCMOS power amplifier based on the simulation of bond wires

针对射频识别技术的应用,该文设计了一款全集成的射频功率放大器.该功率放大器的中心工作频率为915MHz,采用0.18μm Si Ge Bi CMOS工艺的两级单端结构.由于键合线的寄生效应会造成功率放大器的输出功率和效率的减小,本文利用HFSS(High Frequency Simulator Structure)软件建立和分析了键合线的模型,并利用ADS(Advanced Design System)软件拟合仿真数据得到了键合线的等效电路.在功率放大器的仿真中,利用键合线的等效电路来模拟键合线的寄生效应,在此基础上优化电路,最终芯片的面积为(1.6×1.2)mm^2.后仿结果表明,在3.3 V的电源电压下,在860 MHz^960 MHz的工作频段类,输入回波损耗小于-12 d B,输出回波损耗小于-15 d B.功率放大器的1 d B压缩点的输出功率为23 d Bm,功率附加效率(Power-Added Efficiency,PAE)大于20%,功率增益为17.8 d B.

A fully-integrated Si Ge Bi CMOS Power Amplifier（PA） is presented for the application of Radio Frequency Identification（RFID）technology. It is operated at a frequency of 915 MHz,which is based on 0.18 μm Si Ge Bi CMOS process of two-stage single-ended structure. The establishment and analysis of bond wires,model using HFSS and data fitting using ADS obtaining an equivalent circuit of the bond wires are presented because bond wires,parasitic effects will decrease output power and efficiency of PA. In the design of the power amplifier,using the equivalent circuit of bond wires to simulate the bond wires′ parasitic and the chip area was（1.6 × 1.2）mm^2. The post simulation results show that,in band of 860 ~ 960 MHz,the input return loss S11 of less than-12 d B and the output return loss S22 of less than-15 d B. The PA exhibits output power of 23 d Bm,the PAE more than of 20%,and the power gain of 17.8 d B at the output 1 d B compression point.