一种低开销加固锁存器的设计

Design of a Low Cost Radiation Hardened Latch

针对单粒子翻转问题,设计了一种低开销的加固锁存器。在输出级使用钟控C单元,以屏蔽锁存器内部节点的瞬态故障;在输出节点所在的反馈环上使用C单元,屏蔽输出节点上瞬态故障对电路的影响;采用了从输入节点到输出节点的高速通路设计,延迟开销大幅降低。HSPICE仿真结果表明,相比于FERST,SEUI,HLR,Iso-DICE锁存器,该锁存器的面积平均下降23.20%,延迟平均下降55.14%,功耗平均下降42.62%。PVT分析表明,该锁存器的性能参数受PVT变化的影响很小,性能稳定。

A low cost radiation hardened latch was designed to deal with the single event upset. The proposed latch employed a clocked C-element at the output stage to tolerate the internal nodes transient fault. Meanwhile, a C-element was employed at the feedback loop of the output node to tolerate the negative effect of transient fault. The proposed latch adopted a high speed path from input to output and made the delay reduce significantly. The HSPICE simulation results showed that the proposed structure achieved 23.20% area reduction, 55.14% delay reduction and 42.62% power reduction on average compared with that of FERST latch, SEUI latch, HLR latch, Iso-DICE latch. The circuit achieved stable performance under PVT variations.