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生长界面对掺钒SiC电阻率的影响 被引量:1

Effect of the Growth Interface Shape on the Resistivity in V-doped SiC Crystal
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摘要 碳化硅(SiC)单晶多采用物理气相传输(PVT)法及籽晶顶置工艺生长,典型的生长界面包括略凹、近平微凸、略凸三种生长界面,在100 mm(4英寸)掺钒(V)半绝缘4H-SiC单晶生长过程中,需要研究不同生长界面对SiC单晶电阻率的影响,得到合适的生长界面。在近似的生长条件下,采用略凹、近平微凸、略凸三种生长界面生长出100 mm掺V半绝缘4H-SiC单晶,加工后进行了电阻率测试、应力等测试,结果表明近平微凸生长界面易于调整掺杂浓度,晶体缺陷少,适合生长电阻率均匀的掺V半绝缘4H-Si C单晶,且晶体出片率高。 There are three typical growth interface shapes in top-seeded growth of Silicon Carbide(SiC)crystal by Physical Vapor Transport(PVT) method. They are concave interface, slightly convex near horizontal interface and convex interface. We growed V-doped 4 inch SiC crystals by three different growth interface shapes under similar growth conditions. These crystals has been machininged to wafers.We tested wafes' resistivity and stresses. The test results show that using slightly convex near the horizontal growth interface during the process can easily adjust doping concentration and reduce defects in SiC crystal. And the 4H-SiC crystal will have uniform resistivity with high output of high quality SiC wafers.
出处 《电子工业专用设备》 2016年第6期37-39,69,共4页 Equipment for Electronic Products Manufacturing
基金 国家自然科学基金(项目号61404117) 国家高技术研究发展计划(项目号2014AA041401)
关键词 掺钒半绝缘 4H-SIC 电阻率 应力 V-doped semi-insulating 4H-SiC Resistivity Stresses
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