基于FPGA的动态部分可重构智能I/O接口设计与实现

Design and Implementation of Dynamic Partial Reconfiguration Intelligent I/O Interface Based on FPGA

由ASIC芯片实现的总线接口中,存在装备计算机配置冗杂、软硬件升级不灵活、芯片垄断和停产、体积功耗瓶颈日趋明显等问题。为此,基于Xilinx公司的ZYNQ-7000系列现场可编程门阵列,设计部分可重构的智能I/O接口。采用可编程片上系统技术,基于Vivado2014.4和Peta Linux开发环境和开发工具,以RS232,RS422,CAN总线接口为例,通过TCP/IP网络数据包切换总线接口配置指令,动态切换对应的局部比特流文件,以按需通信方式实现各接口的实际配置。仿真实验结果表明,部分可重构技术与片上系统技术的结合使得产品设计流程更加灵活,可降低产品对硬件的依赖度和更新换代的成本,减小资源和功耗的消耗,在一定程度上提升产品的安全性及可靠性。

There are problems of miscellaneous computer congifuration,inflexible hardware and software upgrades,chip monopoly and stopping production,and increasingly evident bottleneck of volume and power consumption in bus interface implemented by ASIC chip.To solve these problems,this paper introduces the design of partial reconfiguration intelligent I/O interface based on the ZYNQ-7000 series Field Programmable Gate Array（FPGA） from Xilinx.By using programmable System-on-Chip（SoC） technology,based on PetaLinux development environment and Vivado2014.4 development tool,taking RS232,RS422 and CAN bus interfaces as example,the user can switch the bus interface configuration instructions via TCP/IP network data packet,and dynamically switch the corresponding local bit stream file,thus achieving the actual configuration of each interface and on-demand communication.Simulation results show that the combination of partial-reconfiguration technology and SoC technology makes the product design process more flexible and reduces the product’s dependence on hardware and update cost as well as the consumption of resources and power.In a certain extent,it also enhances the product safety and reliability.