基于UltraFlex的多时钟域电路测试方法

Test Method for UltraFlex-based Multiple Clock Domain Circuit

介绍了一种在UltraFlex系统上进行多时钟域电路测试的方法,利用了UltraFlex系统自身硬件设计的特点和VBT,解决系统在多时钟电路频率比较高的情况下最小公倍数频率超过测试系统规格的问题。此方法通用,可进行不规则多时钟ASIC的测试,降低了设计和测试人员测试算法设计的难度,提高了设计和测试开发速度。

The article introduces a test method for multiple clock domain circuit in UltraFlex system. The method refers to UltraFlex hardware design and VBT to solve the problem that the lowest common multiple exceeds test system capacity when the multiple clock domain frequency is high. The method is universally applicable for multiple clock domain ASICs.It reduces the workload of design and test algorithm design and accelerates the design and test process.