一种DPLL的FPGA实现及其特性仿真

Design and Simulation Implementation of a Novel Digital PLL Based on FPGA

基于VHDL语言设计了一种面向声波定位的数字锁相环。介绍了数字锁相环路主要模块的结构,利用FPGA实现了这种数字锁相环。通过理论与仿真分析的方法对其性能进行了研究,其技术参数符合声波多普勒频率偏测量要求。

An implementation method of digital phase- locked loop（ DPLL） based on VHDL was introduced deeply in this paper. The DPLL is fit for locating by sound wave. The design method and simulation result of DPLL was introduced. And the DPLL was completed by FPGA. The simulation result shows that the lock- time of DPLL was shortened and the phase dithering was decreased when it was used in voice frequency system. It is fit for measured to Doppler frequency.