摘要
针对电源噪声在时钟电路的锁相环中引起的抖动问题,通过分析周期抖动和相位抖动与电源噪声间的关系,提出了用于预测电源噪声引起的锁相环抖动峰峰值的计算公式。文中预测的抖动峰峰值与HSPICE的仿真结果间的误差最大为3%,说明了文中公式的有效性。
In terms of the jitter in phase locked phase loop caused by the power supply noise,the equation used to predict the peak- to- peak jitter induced by power supply noise is presented through analyzing the relation between the power supply noise,the phase jitter and the period jitter. The maximum error between the results predicted by the equation presented in this paper and simulated by HSPICE is 3%,which verifies the accuracy of this equation.
出处
《电子科技》
2016年第7期102-105,共4页
Electronic Science and Technology
关键词
锁相环
电源噪声
周期抖动
phase clocked loop
power supply noise
period jitter
