面向DVB-S2标准LDPC码的高效编码结构

Efficient Encoding Architecture for LDPC Code Based on DVB-S2 Standard

面向DVB-S2标准LDPC码,该文旨在实现一种基于FPGA的高效编码结构,提出一种快速流水线并向递归编码算法,可以显著提高编码数据信息吞吐率。同时,通过并向移位运算和并向异或运算的处理结构计算编码中间变量及校验位信息,在提高编码并行度的同时可有效减少存储资源的消耗。此外,针对动态自适应编码的情况优化了LDPC码编码存储结构,有效复用了数据存储单元和RAM地址发生器,进一步提高FPGA的硬件逻辑资源利用率。针对DVB-S2标准LDPC码,基于Stratix IV系列FPGA的验证结果表明,所提编码结构在系统时钟为126.17 MHz时,编码数据信息吞吐率达20 Gbps以上。

For DVB-S2 standard LDPC code, to achieve an efficient encoding architecture based on FPGA, a fast pipeline parallel and recursive encoding algorithm is proposed which can significantly improve encoding speed and improve the encoding data rate of information throughput. At the same time, the parallel shift operation and parallel XOR processing structure is introduced to calculate code intermediate variable. It can effectively improve the encoding parallel degree and reduce the occupancy volume of storage resources. In addition, according to dynamic adaptive encoding, the storage structure and effective reuse of data storage unit and the RAM address generator are optimized. In this case, the utilization of FPGA resources is further improved. The experiment based on Stratix IV series FPGA for DVB-S2 standard LDPC code, shows that the proposed method can achieve system clock frequency of 126.17 MHz and encoding data rate of information throughput of more than 20 Gbps.