基于自偏置技术的高速SERDES芯片PLL设计

PLL Design of High Speed SERDES Chips Based on Self-biased Technique

设计了适用于宽输入范围的Ser Des芯片的锁相环电路,采用自偏置技术,有较宽的输入参考频率范围,不需要外加偏置电路,而且环路带宽能够跟随输入参考频率变化,对噪声有良好的抑制作用。环形VCO占用面积小、频率调节范围宽,并且能够很容易的产生Ser Des中CDR所需要的多相位时钟。采用TSMC-0.25μm CMOS工艺实现了该PLL的设计,工作频率范围是1.6-2.7GHz,并成功应用于一款SERDES芯片中。

The Ser Des chip phase- locked loop circuit for wide input range is designed in this paper,which uses self- biased technology,in wide range of input reference frequency,without external bias circuit,and the loop bandwidth changes with input reference frequency to perform good inhibitory effect for the noise. The small footprint annular VCO has wide frequency adjustment range and easily produces the multi- phase clock required by CDR Ser Des. TSMC- 0. 25μm CMOS process,successfully applied in a SERDES chip,is used to achieve the PLL design in the operating frequency range of 1. 6- 2. 7GHz.